我尝试在Windows PC上使用ActiveState TCL来运行以下TCL。看起来我在#\（.* ？\）及其匹配的greedy到下一个语句中。你知道我做错了什么或者怎么补救吗

proc extract_verilog_instances {text} {

    set rexp {(\w+)\s+(\#\s*\((?:.*?)\)\s*)?(\w+(?:\[\d+\])?)\s*\(}

    # rexp will match any of the following statement types:
    #
    #   module_name instance_name ( 
    #   module_name instance_name[0] (
    #   module_name #(parameter1, parameter2) instance_name (
    #   module_name #(parameter1, parameter2) instance_name[0] (

    set regrun [regexp -inline -all -indices -expanded $rexp $text]

    foreach {m0 m1 m2 m3} $regrun {
        set start_index    [lindex $m0 0]
        set end_index      [lindex $m0 1]
        set module   [string range $text [lindex $m1 0] [lindex $m1 1]]
        set instance [string range $text [lindex $m3 0] [lindex $m3 1]]

       puts "module:$module instance:$instance"
    }
}

set vlog {
    
    second_module #(2) inst2 (.in2(sig2), .out2(sig3));

    third_module inst3 (.in3(sig3), .out3(sig4));

    fourth_module #(.in4_clk_freq(50), .in4_rst_val(1'b0)) inst4 (.in4_clk(clk), .in4_rst(rst), .in4_in1(sig4), .in4_in2(sig5), .out4(sig6));
}

extract_verilog_instances $vlog

proc extract_verilog_instances5 $vlog

预期输出：

module:second_module instance:inst2
module:third_module instance:inst3
module:forth_module instance:inst4

实际产量：

module:second_module instance:inst4